The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2012

Filed:

Oct. 26, 2010
Applicants:

Michael Scott, Rochester, NY (US);

Sandhya Dwarkadas, Pittsford, NY (US);

Arrvindh Shriraman, Rochester, NY (US);

Virendra Marathe, Rochester, NY (US);

Michael F. Spear, Rochester, NY (US);

Inventors:

Michael Scott, Rochester, NY (US);

Sandhya Dwarkadas, Pittsford, NY (US);

Arrvindh Shriraman, Rochester, NY (US);

Virendra Marathe, Rochester, NY (US);

Michael F. Spear, Rochester, NY (US);

Assignee:

University of Rochester, Rochester, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a transactional memory technique, hardware serves simply to optimize the performance of transactions that are controlled fundamentally by software. The hardware support reduces the overhead of common TM tasks—conflict detection, validation, and data isolation—for common-case bounded transactions. Software control preserves policy flexibility and supports transactions unbounded in space and in time. The hardware includes 1) an alert-on-update mechanism for fast software-controlled conflict detection; and 2) programmable data isolation, allowing potentially conflicting readers and writers to proceed concurrently under software control.


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