The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2012
Filed:
Jul. 30, 2010
Kotaro Watanabe, Chiba, JP;
Tomohiro Oka, Chiba, JP;
Teruo Suzuki, Chiba, JP;
Seiko Instruments Inc., Chiba, JP;
Abstract
Provided are a memory circuit having a small circuit scale and a voltage detection circuit including the memory circuit. An NMOS transistor () is in an off state during loading and writing and is in an on state during reading. An NMOS transistor () is turned on when a high level input is received and turned off when a low level input is received. An NMOS transistor () is in the off state during loading and writing and is in the on state during reading. A PMOS transistor () is in the on state during loading and is in the off state during writing and reading. A PMOS transistor () is turned off when the high level input is received during loading, is turned on when the low level input is received during loading, and is in the on state during writing and reading.