The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2012

Filed:

Oct. 06, 2010
Applicants:

Yasutoshi Tasaka, Kanagawa, JP;

Yohei Nakanishi, Nara, JP;

Masakazu Shibasaki, Mie, JP;

Tsuyoshi Kamada, Kanagawa, JP;

Hidefumi Yoshida, Kanagawa, JP;

Hideaki Tsuda, Kanagawa, JP;

Inventors:

Yasutoshi Tasaka, Kanagawa, JP;

Yohei Nakanishi, Nara, JP;

Masakazu Shibasaki, Mie, JP;

Tsuyoshi Kamada, Kanagawa, JP;

Hidefumi Yoshida, Kanagawa, JP;

Hideaki Tsuda, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F 1/136 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to a liquid crystal display device and provides a liquid crystal display device which can achieve high display quality. A liquid crystal display device is provided with first and second TFTs each having a gate electrode connected to an nth gate bus line and a drain electrode connected to a drain bus line; a first pixel electrode connected to a source electrode of the first TFT; a second pixel electrode connected to a source electrode of the second TFT; a third TFT having a gate electrode connected to an (n+1)th gate bus line and a source electrode connected to the second pixel electrode; and a buffer capacitance portion having a buffer capacitance electrode which is formed in the same layer as the first and second pixel electrodes and is connected to a drain electrode of the third TFT and a buffer capacitance electrode connected to a storage capacitance bus line. The buffer capacitance portion establishes capacitive coupling between the drain electrode of the third TFT and the storage capacitance bus line.


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