The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2012

Filed:

Nov. 26, 2007
Applicants:

Yuji Furumura, Yokohama, JP;

Naomi Mura, Tokyo, JP;

Shinji Nishihara, Kokubunji, JP;

Katsuhiro Fujino, Yokohama, JP;

Katsuhiko Mishima, Yokohama, JP;

Susumu Kamihashi, Yokohama, JP;

Inventors:

Yuji Furumura, Yokohama, JP;

Naomi Mura, Tokyo, JP;

Shinji Nishihara, Kokubunji, JP;

Katsuhiro Fujino, Yokohama, JP;

Katsuhiko Mishima, Yokohama, JP;

Susumu Kamihashi, Yokohama, JP;

Assignee:

Philtech, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing RF powder wherein the RF powder is composed of a large amount of particles and used as collective RF powder (a powdery entity); and a large amount of RF powder particles can be obtained from a wafer in a stable manner and at a high yield is provided. The method for manufacturing RF powder is a method for manufacturing RF powder composed of a large amount of particleseach having a substrateand a magnetic coupling circuit device. This method includes a step Sof forming many antenna circuit deviceson a wafer; a gas dicing step Sfor drawing dicing grooves on a wafer to locate positions of separation of magnetic coupling circuit devices; a protection film formation step Sfor coating surrounding areas of the magnetic coupling circuit devices with a protection film; a reinforcement step Sfor attaching the wafer to a supporting plate using an adhesive sheet; a grinding step Sfor grinding the backside of the wafer until the dicing grooves are reached; and a separation step Sfor separating the circuit devices by removing the supporting plate.


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