The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8176457 B1

PDF
Full Text
Expired
Date of Patent:
May. 08, 2012

Filed:

Sep. 24, 2007
Applicants:

Yoshiyuki Kato, Kawasaki, JP;

Hisashi Aoyama, Kawasaki, JP;

Inventors:

Yoshiyuki Kato, Kawasaki, JP;

Hisashi Aoyama, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin-assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. A pin-swap processing unit retrieves pin swap information from a package-designing CAD apparatus, and reflect the pin swap in the symbol library, the FPGA information, a circuit diagram, and a constrained condition.


Find Patent Forward Citations

Kato, Yoshiyuki. (2012). Apparatus and method updating diagram of circuit based on pin swap performed in package design with respect to pld (U.S. Patent No. 8176457). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8176457

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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