The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2012
Filed:
Sep. 11, 2009
Kai Yang, San Jose, CA (US);
Tayung Liu, Sunnyvale, CA (US);
Furshing Tsai, San Jose, CA (US);
Ting Shih Ang, Hsinchu, TW;
Chih Neng Hsu, Zu-Dong Township, TW;
Jun Zhao, Pleasanton, CA (US);
Kai Yang, San Jose, CA (US);
Tayung Liu, Sunnyvale, CA (US);
Furshing Tsai, San Jose, CA (US);
Ting Shih Ang, Hsinchu, TW;
Chih Neng Hsu, Zu-Dong Township, TW;
Jun Zhao, Pleasanton, CA (US);
Springsoft USA, Inc., San Jose, CA (US);
Abstract
A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.