The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2012
Filed:
Mar. 10, 2010
Ken Matsubara, Tokyo, JP;
Hideo Kasai, Tokyo, JP;
Kenji Kawada, Tokyo, JP;
Makoto Mizuno, Tokyo, JP;
Ken Matsubara, Tokyo, JP;
Hideo Kasai, Tokyo, JP;
Kenji Kawada, Tokyo, JP;
Makoto Mizuno, Tokyo, JP;
Renesas Electronics Corporation, Kawasaki-shi, JP;
Abstract
This invention is to reduce the number of memory gate drivers, while lessening the number of times of disturb occurrence in a memory array configuration that implements writing in small byte units. A memory array comprises a plurality of sub-arrays, MG transfers, SL drivers, and CG drivers. Each sub-array includes a plurality of memory gate lines, control gate lines, source lines, and bit lines. Memory cells are arranged in positions of intersections of these lines. The control gate lines, CG drivers, source lines, and SL drivers are common to the sub-arrays, whereas the memory gate lines and MG buffer circuits are provided for each sub-array. Thereby, the units in which data is written are decreased and adverse effects of disturb are reduced without increasing the circuit size of the memory array.