The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2012

Filed:

Sep. 15, 2008
Applicants:

Fabio Sebastiano, Eindhoven, NL;

Lucien Johannes Breems, Eindhoven, NL;

Raf Lodewijk Jan Roovers, Wommelgem, BE;

Inventors:

Fabio Sebastiano, Eindhoven, NL;

Lucien Johannes Breems, Eindhoven, NL;

Raf Lodewijk Jan Roovers, Wommelgem, BE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a circuit and a method for automatic common-mode rejection calibration in a differential conversion system and unbalance compensation for balancing the operation point of a circuit in the signal path and for enhancing the common-mode rejection. The circuit for automatic common-mode rejection calibration in a differential conversion system comprises an analog input stage for an analog input signal (), an analog-digital-converter () for converting an analog signal () into its digital representation (), a digital block () arranged to adapt said digital representation () of a portion of a DC offset of said analog input signal () in accordance with whether said analog input signal () is in a predetermined input range of said analog-digital-converter (), and a digital-analog-converter () arranged in a feedback path () from said digital block () to subtraction means () of said analog input stage for converting a digital signal () into an analog output signal (), wherein said analog output signal () is subtracted from said analog input signal () resulting in said analog signal ().


Find Patent Forward Citations

Loading…