The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2012

Filed:

Mar. 21, 2011
Applicants:

Mark Van Der Heijden, Eindhoven, NL;

Mustafa Acar, Eindhoven, NL;

Jan Sophia Vromans, Maastricht, NL;

Melina Apostolidou, Enschede, NL;

Inventors:

Mark van der Heijden, Eindhoven, NL;

Mustafa Acar, Eindhoven, NL;

Jan Sophia Vromans, Maastricht, NL;

Melina Apostolidou, Enschede, NL;

Assignee:

NXP B.V., , NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/68 (2006.01);
U.S. Cl.
CPC ...
Abstract

Various embodiments relate to a reconfigurable integrated digital Chireix out-phasing power amplifier for use in high power base stations is described and a related method of said design. The power amplifier may include a power transistor circuitry having plurality of power transistors and shunt-series circuitry (LC, LC), a broadband combiner having Chireix compensation elements, and an impedance matching filter. In one embodiment, the power amplifier is implemented in a real switch-mode to facilitate integration of the Chireix compensation elements so as to make the Chireix power amplifier tunable. A method of driving Chireix power amplifier structure is also described. In some embodiments, a variable supply voltage may power the transistor circuitry based on the desired output power of the Chireix power amplifier. In some embodiments, the variable supply voltage may depend upon an out-phasing angle between the two drivers in the transistor circuitry.


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