Buffer circuit with improved duty cycle distortion and method of using the same

Abstract

An improved buffer circuit and method for minimizing (or altogether eliminating) duty cycle distortion between input and output signals of the buffer circuit are provided herein. In general, the improved buffer circuit essentially decouples the charging and discharging current paths of the buffer circuit from a reference voltage supplied to the buffer circuit. This ensures substantially equal time delays between rising and falling edges of the input and output signals, thereby decreasing duty cycle distortion and maintaining a maximum operating frequency of the buffer circuit, even when the reference voltage approaches a transistor threshold voltage. In addition, the improved method may include forwarding an input signal with an input duty cycle onto mutually connected gate terminals of a pair of pull-down transistors, and activating/inactivating at least one of the pair of pull-down transistors during logic high and logic low voltage values of the input duty cycle, respectively. In this manner, the method provides an output signal with an output duty cycle that is substantially equal to the input duty cycle.