The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2012

Filed:

Oct. 29, 2006
Applicants:

Joost Melai, Enschede, NL;

Erwin Hijzen, Blanden, BE;

Philippe Meunier-beillard, Kortenberg, BE;

Johannes Josephus Theodorus Marinus Donkers, Valkenswaard, NL;

Inventors:

Joost Melai, Enschede, NL;

Erwin Hijzen, Blanden, BE;

Philippe Meunier-Beillard, Kortenberg, BE;

Johannes Josephus Theodorus Marinus Donkers, Valkenswaard, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/331 (2006.01); H01L 21/8222 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to a method of manufacturing a semiconductor device () with a substrate () and a semiconductor body () which is provided with at least one bipolar transistor having an emitter region (), a base region () and a collector region (), wherein in the semiconductor body () a first semiconductor region () is formed that forms one () of the collector and emitter regions () and on the surface of the semiconductor body () a stack of layers is formed comprising a first insulating layer (), a polycrystalline semiconductor layer () and a second insulating layer () in which stack an opening () is formed, after which by non-selective epitaxial growth a further semiconductor layer () is deposited of which a monocrystalline horizontal part on the bottom of the opening () forms the base region () and of which a polycrystalline vertical part (A) on a side face of the opening () is connected to the polycrystalline semiconductor layer (), after which spacers (S) are formed parallel to the side face of the opening () and a second semiconductor region () is formed between said spacers (S) forming the other one () of the emitter and collector regions (). According to the invention the above method is characterized in that before the further semiconductor layer () is deposited, the second insulating layer () is provided with an end portion (A) that viewed in projection overhangs an end portion (A) of the underlying semiconductor layer (). In this way bipolar transistor devices can be obtained with good high frequency properties in a cost effective manner.


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