The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2012
Filed:
Dec. 29, 2010
Christopher J. Petti, Mountain View, CA (US);
Mohamed M. Hilali, Austin, TX (US);
Theodore Smick, Essex, MA (US);
Venkatesan Murali, San Jose, CA (US);
Kathy J. Jackson, Felton, CA (US);
Zhiyong LI, Los Altos, CA (US);
Gopalakrishna Prabhu, San Jose, CA (US);
Christopher J. Petti, Mountain View, CA (US);
Mohamed M. Hilali, Austin, TX (US);
Theodore Smick, Essex, MA (US);
Venkatesan Murali, San Jose, CA (US);
Kathy J. Jackson, Felton, CA (US);
Zhiyong Li, Los Altos, CA (US);
Gopalakrishna Prabhu, San Jose, CA (US);
Twin Creeks Technologies, Inc., San Jose, CA (US);
Abstract
A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating, or by application of a precursor and curing in situ, resulting in a support element which may be, for example, metal, ceramic, polymer, etc. This is in contrast to a rigid or semi-rigid pre-formed support element which is affixed to the lamina following its formation, or to a donor wafer from which the lamina is subsequently cleaved. Fabricating the support element in situ may avoid the use of adhesives to attach the lamina to a permanent support element; such adhesives may be unable to tolerate processing temperatures and conditions required to complete the device. In some embodiments, this process flow allows the lamina to be annealed at high temperature, then to have an amorphous silicon layer formed on each face of the lamina following that anneal. A device may be formed which comprises the lamina, such as a photovoltaic cell.