The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2012
Filed:
May. 05, 2008
David Q. Chow, San Jose, CA (US);
Frank Yu, Palo Alto, CA (US);
Charles C. Lee, Cupertino, CA (US);
Abraham C. MA, Fremont, CA (US);
Ming-shiang Shen, Taipei Hsien, TW;
David Q. Chow, San Jose, CA (US);
Frank Yu, Palo Alto, CA (US);
Charles C. Lee, Cupertino, CA (US);
Abraham C. Ma, Fremont, CA (US);
Ming-Shiang Shen, Taipei Hsien, TW;
Super Talent Electronics, Inc., San Jose, CA (US);
Abstract
A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.