The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2012
Filed:
Jul. 17, 2006
Zeljko Mrcarica, Zurich, CH;
Fabrice Blanc, Crolles, FR;
Zeljko Mrcarica, Zurich, CH;
Fabrice Blanc, Crolles, FR;
NXP B.V., Eindhoven, NL;
Abstract
Integrated circuit () comprising several different voltage rails (Vto V) and an on-chip ESD protection circuit. The ESD protection circuit comprises at least one group () of ESD clamp devices (C-C). The ESD clamp devices (C-C) are arranged in a ladder-configuration. This ladder-configuration is characterized in that there is one of the ESD clamp devices interposed between each of the power rails (Vto V) and the respective power rail having a next lower voltage. Due to this arrangement an ESD current path is defined between each one of the power rails and the power rail having the next lower voltage. The ESD clamp devices (C-C) are off under normal power operation of the integrated circuit ().