The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2012
Filed:
Feb. 04, 2009
Lawrence David Smith, San Jose, CA (US);
Quoc Cuong D. Nguyen, San Jose, CA (US);
Ravindra Reddy Gali, San Jose, CA (US);
Lawrence David Smith, San Jose, CA (US);
Quoc Cuong D. Nguyen, San Jose, CA (US);
Ravindra Reddy Gali, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A method of calculating a system power distribution network impedance is presented. The impedance calculation calculates the impedance as separate elements of the printed circuit board (PCB). An approximation of the power and ground via inductance of the printed circuit board is made based on the configuration of the printed circuit board. The decoupling capacitors of the PCB are modeled as a parallel combination of inductors, capacitors, and resistors, and the parallel combination is used to calculate the impedance. In addition to the impedance associated with the decoupling capacitors, the method calculates an inductance associated with a mounting orientation of the decoupling capacitors. The power and ground planes of the printed circuit board have an associated capacitance and inductance, which is calculated. The resultant simulated impedance profile illustrating the board configuration impedance over a frequency range is displayed.