The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2012

Filed:

Feb. 03, 2009
Applicants:

Liang-wei Huang, Taipei, TW;

Chih-yung Shih, Taipei, TW;

Shieh-hsing Kuo, Taipei County, TW;

Inventors:

Liang-Wei Huang, Taipei, TW;

Chih-Yung Shih, Taipei, TW;

Shieh-Hsing Kuo, Taipei County, TW;

Assignee:

Realtek Semiconductor Corp., Science Park, HsinChu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A network signal processing circuit includes a first signal processing module, a first sampling rate converter, a second signal processing module, a second sampling rate converter and a timing controller. The first signal processing module is utilized for processing a network signal to output a first processed signal. The first sampling rate converter is utilized for performing signal frequency conversion on the first processed signal according to a first clock timing adjusting signal and outputting a first converted signal. The second signal processing module is utilized for processing the first converted signal to output a second processed signal. The second sampling rate converter is utilized for performing signal frequency conversion on the second processed signal according to a second clock timing adjusting signal and outputting a second converted signal. The timing controller is utilized for generating the first and second clock timing adjusting signals.


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