The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2012
Filed:
Feb. 02, 2009
Noam Eshel, Pardesiyya, IL;
Zeituni Golan, Kfar Saba, IL;
Noam Eshel, Pardesiyya, IL;
Zeituni Golan, Kfar Saba, IL;
Pixim Israel Ltd., Ra'anana, IL (US);
Abstract
A device that includes a pixel array, an interfacing circuit and a sample and hold circuit. The interfacing circuit directs to at least one pixel of the pixel array a sampled voltage that is outputted from the sample and hold circuit. The sample and hold circuit includes an NMOS transistor, a bootstrap circuit, a capacitor, sample phase switches and hold phase switches. During the sample phase the source of the NMOS transistor receives the input voltage; the gate of the NMIS transistor receives, from the bootstrap circuit a gate voltage that exceeds a supply voltage and a capacitor of the sample and hold circuit is charged to the input voltage to provide the sampled voltage. During a hold phase the capacitor stores the sampled voltage; the gate, source and drain of the NMOS transistor are maintained at the same potential and the source of the NMOS transistor is disconnected from an input port through which the input voltage was provided.