Circuitry and method for preventing base-emitter junction reverse bias in comparator differential input transistor pair

Abstract

A differential input circuit (-) includes first (Q) and second (Q) input transistors having control electrodes coupled to first (V) and second (V) input signals, respectively. A pass transistor (P) is coupled between first electrodes of the first and second input transistors. First (N) and second (N) level shift transistors have control electrodes coupled to the first and second input signals, respectively. A voltage selector circuit () selects a voltage on a first electrode of one of the first and second level shift transistors according to which is at a higher voltage, and produces a corresponding control voltage (V) on a control electrode of the pass transistor so as to limit a voltage difference between the first electrode and the control electrode of the first input transistor (Q) when it is turned off in response to a large difference between the first and second input signals.