The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2012

Filed:

Jun. 09, 2009
Applicants:

Ji-young Kim, Los Angeles, CA (US);

Kang L. Wang, Santa Monica, CA (US);

Yong-jik Park, Gyeonggi-do, KR;

Jeong-hee Han, Gyeonggi-do, KR;

Augustin Jinwoo Hong, Los Angeles, CA (US);

Inventors:

Ji-Young Kim, Los Angeles, CA (US);

Kang L. Wang, Santa Monica, CA (US);

Yong-Jik Park, Gyeonggi-do, KR;

Jeong-Hee Han, Gyeonggi-do, KR;

Augustin Jinwoo Hong, Los Angeles, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentially and alternatingly stacked. Thereafter, side surfaces of the first mold patterns are selectively etched to form undercut regions between the second mold patterns. Then, a semiconductor layer is formed to cover a surface of the mold structure where the undercut regions are formed, and gate patterns are formed, which fill respective undercut regions where the semiconductor layer is formed.


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