The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2012
Filed:
Jan. 17, 2008
Chaitra M. Bhat, Bangalore, IN;
Chandrika Madhwacharya, Bangalore, IN;
Atsushi Sugai, Kyoto, JP;
Toshihiko Yokota, Kyoto, JP;
Chaitra M. Bhat, Bangalore, IN;
Chandrika Madhwacharya, Bangalore, IN;
Atsushi Sugai, Kyoto, JP;
Toshihiko Yokota, Kyoto, JP;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.