System for analyzing sensitivity of parasitic capacitance to variation of semiconductor design parameters

Abstract

A sensitivity analysis system has a memory device in which an interconnect structure data indicating an interconnect structure included in a semiconductor device is stored. The interconnect structure has: a main interconnection; and a contact structure electrically connected to the main interconnection and extending toward a semiconductor substrate. Parameters contribute to parasitic capacitance of the interconnect structure, and variation of each parameter from a design value caused by manufacturing variability is represented within a predetermined range. The sensitivity analysis system further has: a parameter setting unit that sets the variation to a plurality of conditions within the predetermined range; a capacitance calculation unit that calculates the parasitic capacitance of the interconnect structure in each of the plurality of conditions; and a sensitivity analysis unit that analyzes, based on the calculated parasitic capacitance, response of the parasitic capacitance to variation of the each parameter.