The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2012

Filed:

Apr. 22, 2008
Applicants:

Seong-ook Jung, Seoul, KR;

Jisu Kim, Seoul, KR;

Jee-hwan Song, Seoul, KR;

Seung H. Kang, San Diego, CA (US);

Sei Seung Yoon, San Diego, CA (US);

Inventors:

Seong-Ook Jung, Seoul, KR;

Jisu Kim, Seoul, KR;

Jee-Hwan Song, Seoul, KR;

Seung H. Kang, San Diego, CA (US);

Sei Seung Yoon, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermined design constraint of the resistance based memory circuit and selecting a second parameter based on a second predetermined design constraint of the resistance based memory circuit. The method further includes performing an iterative methodology to adjust at least one circuit parameter of a sense amplifier portion of the resistance based memory circuit by selectively assigning and adjusting a physical property of the at least one circuit parameter to achieve a desired sense amplifier margin value without changing the first parameter or the second parameter.


Find Patent Forward Citations

Jung, Seong-Ook. (2012). System and method of resistance based memory circuit parameter adjustment (U.S. Patent No. 8161430). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8161430

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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