The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2012
Filed:
Feb. 15, 2008
Michael Laisne, Encinitas, CA (US);
Songlin Zuo, San Diego, CA (US);
Hailong Cui, San Diego, CA (US);
Xiangdong Pan, San Diego, CA (US);
Triphuong Nguyen, Escondido, CA (US);
Michael Laisne, Encinitas, CA (US);
Songlin Zuo, San Diego, CA (US);
Hailong Cui, San Diego, CA (US);
Xiangdong Pan, San Diego, CA (US);
Triphuong Nguyen, Escondido, CA (US);
QUALCOMM, Incorporated, San Diego, CA (US);
Abstract
Quiescent supply current (I) verification, prediction, and debugging of low power semiconductor devices are enhanced by Idefect diagnosis. If all Ipatterns fail verification, per module analysis is performed to sort out potential module design issues or cell constraint issues. For issues of missing constraints, and cell design or implementation issues leading to extra leakage that could be avoided by adding constraints, there are usually Ipatterns that correlate with expectations, and patterns that do not, due to the random nature of unconstrained scan cell values as determined by the pattern generation tool. Differentiating good and bad Ipatterns can identify root causes of Iissues and additional constraints to fix the bad Ivectors. These verification procedures are achieving Itest success and short time to market, as well as significantly faster time to volume and improved yields because of having a higher quality and better-controlled Itest.