The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2012

Filed:

Dec. 20, 2007
Applicants:

Vinayak Tilak, Niskayuna, NY (US);

Alexei Vertiatchikh, Schenectady, NY (US);

Kevin Sean Matocha, Rexford, NY (US);

Peter Micah Sandvik, Clifton Park, NY (US);

Siddharth Rajan, Goleta, CA (US);

Inventors:

Vinayak Tilak, Niskayuna, NY (US);

Alexei Vertiatchikh, Schenectady, NY (US);

Kevin Sean Matocha, Rexford, NY (US);

Peter Micah Sandvik, Clifton Park, NY (US);

Siddharth Rajan, Goleta, CA (US);

Assignee:

General Electric Company, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.


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