The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2012
Filed:
Apr. 11, 2006
Kenji Kumagai, Kawasaki, JP;
Kenji Kumagai, Kawasaki, JP;
Fujitsu Semiconductor Limited, Yokohama, JP;
Abstract
A plurality of cells are disposed in a chip region and wires are disposed between the cells in order to connect the cells over a plurality of layout steps. The layout method comprises (1) a placement restricted region placement step for disposing, in the chip region, a placement restricted region in which placement of predetermined cell types is prohibited or permitted in accordance with different layout steps, (2) a first layout step for disposing a desired cell in the chip region in conformity with the cell types that are prohibited or permitted in accordance with the first layout step of the disposed placement restricted region, and (3) a second layout step for disposing a desired cell in the chip region in conformity with the cell types that are prohibited or permitted in accordance with the second layout step of the disposed placement restricted region.