The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2012
Filed:
Jan. 27, 2009
Shayan Zhang, Austin, TX (US);
James D. Burnett, Austin, TX (US);
Prashant U. Kenkare, Austin, TX (US);
Hema Ramamurthy, Austin, TX (US);
Andrew C. Russell, Austin, TX (US);
Michael D. Snyder, Cedar Park, TX (US);
Shayan Zhang, Austin, TX (US);
James D. Burnett, Austin, TX (US);
Prashant U. Kenkare, Austin, TX (US);
Hema Ramamurthy, Austin, TX (US);
Andrew C. Russell, Austin, TX (US);
Michael D. Snyder, Cedar Park, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that include non-functional bits are not used. Much of the memory may remain functional and use is retained. When the voltage is increased, the portions of the memory that were not used because of being non-functional due to the reduced power supply voltage may then be used again. This is particularly useful in a cache where the decrease in available memory due to power supply voltage reduction can be implemented as a reduction in the number of ways. Thus, for example an eight way cache can simply be reduced to a four way cache when the power is being reduced or endurance increased.