The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2012

Filed:

Jan. 14, 2010
Applicant:

Hiroshi Ito, Yokohama, JP;

Inventor:

Hiroshi Ito, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/18 (2006.01);
U.S. Cl.
CPC ...
Abstract

A device includes a memory cell array and a control circuit, the memory cell array including word-lines, bit-lines, and memory cells arranged at the intersections of the word-lines and the bit-lines, each memory cell including an electrically programmable antifuse element. The control circuit may perform, as a first step, applying a programming voltage to one of the word-lines while applying a ground voltage to bit-lines each connected to respective selected memory cells, and as a second step, after the first step, keeping one of the one word-lines at the programming voltage while concurrently reading the electrical states of the selected memory cells, and according to the read electrical states, applying the ground voltage again to a bit-line connected to an unprogrammed selected memory cell after the first step, and applying a voltage higher than the ground voltage to a bit-line connected to a programmed selected memory cell after the first step.


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