The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2012
Filed:
Mar. 13, 2009
Masahiro Koike, Yokohama, JP;
Yuichiro Mitani, Kanagawa-Ken, JP;
Tatsuo Shimizu, Tokyo, JP;
Naoki Yasuda, Yokohama, JP;
Yasushi Nakasaki, Yokohama, JP;
Akira Nishiyama, Yokohama, JP;
Masahiro Koike, Yokohama, JP;
Yuichiro Mitani, Kanagawa-Ken, JP;
Tatsuo Shimizu, Tokyo, JP;
Naoki Yasuda, Yokohama, JP;
Yasushi Nakasaki, Yokohama, JP;
Akira Nishiyama, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A nonvolatile semiconductor memory apparatus includes: a source and drain regions formed at a distance from each other in a semiconductor layer; a first insulating film formed on the semiconductor layer located between the source region and the drain region, the first insulating film including a first insulating layer and a second insulating layer formed on the first insulating layer and having a higher dielectric constant than the first insulating layer, the second insulating layer having a first site performing hole trapping and releasing, the first site being formed by adding an element different from a base material to the second insulating film, the first site being located at a lower level than a Fermi level of a material forming the semiconductor layer; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.