The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2012
Filed:
May. 18, 2009
Hiroyuki Ishii, Kanagawa-ken, JP;
Takafumi Ikeda, Kanagawa-ken, JP;
Hiroyuki Ishii, Kanagawa-ken, JP;
Takafumi Ikeda, Kanagawa-ken, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
According to an aspect of the present invention, there is provided a method for fabricating a nonvolatile semiconductor memory device including a memory cell being formed in a first region of a semiconductor substrate and a periphery circuit being formed in a second region of the semiconductor substrate, including forming a first gate electrode material film over the semiconductor substrate via a first gate insulator in the first region, etching the first gate electrode material film and the first gate insulator using a mask having a first opening in a first element isolation of the first region, etching the semiconductor substrate to a first depth to form a first isolation groove, forming a first insulation isolation layer in the first isolation groove, forming a second insulator on the first insulation isolation layer and on the first gate electrode, removing the second insulator by anisotropic etching, etching an upper portion of the first gate electrode to a second depth to form a first concave portion on the upper portion of the first gate electrode, etching the first side-wall film and the first insulation isolation layer to a depth at a bottom surface of the first concave portion, forming a second gate insulator on the upper portion of the first gate electrode, and forming a second gate electrode material film on the second gate insulator.