The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8151149 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 03, 2012

Filed:

Dec. 30, 2009
Applicants:

Jeong-hun Lee, Gyeonggi-do, KR;

Yong-mi Kim, Gyeonggi-do, KR;

Jeong-tea Hwang, Gyeonggi-do, KR;

Inventors:

Jeong-Hun Lee, Gyeonggi-do, KR;

Yong-Mi Kim, Gyeonggi-do, KR;

Jeong-Tea Hwang, Gyeonggi-do, KR;

Assignee:

Hynix Semiconductor Inc., Gyeonggi-do, KR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver.


Find Patent Forward Citations

Lee, Jeong-Hun. (2012). Semiconductor memory apparatus and method of testing the same (U.S. Patent No. 8151149). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8151149

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