The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2012

Filed:

Jan. 29, 2007
Applicants:

David James Foster, Bellevue, WA (US);

Shon Schmidt, Seattle, WA (US);

David Jaroslav Sebesta, Redmond, WA (US);

Curt Andrew Steeb, Redmond, WA (US);

William J. Westerinen, Issaquah, WA (US);

Zhangwei Xu, Redmond, WA (US);

Todd L. Carpenter, Monroe, WA (US);

Inventors:

David James Foster, Bellevue, WA (US);

Shon Schmidt, Seattle, WA (US);

David Jaroslav Sebesta, Redmond, WA (US);

Curt Andrew Steeb, Redmond, WA (US);

William J. Westerinen, Issaquah, WA (US);

Zhangwei Xu, Redmond, WA (US);

Todd L. Carpenter, Monroe, WA (US);

Assignee:

Microsoft Corporation, Redmond, WA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A computer or other electronic device requiring physical integrity of its components, for example, a pay-per-use computer may use a master security device in communication with a plurality of slave security devices, known as security beans. Each security bean may be given a cryptographic key or keys for use in authenticating communication with the master security device. Each security bean may be coupled to an associated component and may have the ability to disable that associated component. In one embodiment, security bean has an analog switch that may be configured to block or attenuate a critical signal used by the associated component. The security bean may start up in the disable mode and respond to a verified signal from the master security device to enable its corresponding component.


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