The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2012

Filed:

Oct. 27, 2009
Applicants:

Hidemitsu Mori, Kawasaki, JP;

Kazuhiro Takimoto, Kawasaki, JP;

Toshiyuki Shou, Kawasaki, JP;

Kenji Sasaki, Kawasaki, JP;

Yutaka Akiyama, Kawasaki, JP;

Inventors:

Hidemitsu Mori, Kawasaki, JP;

Kazuhiro Takimoto, Kawasaki, JP;

Toshiyuki Shou, Kawasaki, JP;

Kenji Sasaki, Kawasaki, JP;

Yutaka Akiyama, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

To provide a semiconductor device in which an interval between first wells can be shortened by improving a separation breakdown voltage between the first wells and a method for manufacturing the same. A semiconductor device includes a first conductivity type semiconductor substrate, second conductivity type first wellsanddisposed on a surface layer of the semiconductor substratewith a predetermined interval between them, a first conductivity type second welldisposed between the first wellsandon the surface layer of the semiconductor substrateand having an impurity concentration higher than that of the semiconductor substrate, a first conductivity type third wellat least disposed below the second wellin the semiconductor substrateand having an impurity concentration higher than that of the semiconductor substrateand lower than that of the second well, and a first conductivity type fourth wellat least disposed below the third wellin the semiconductor substrateand having an impurity concentration higher than that of the semiconductor substrateand lower than that of the second well


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