The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8148754 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 03, 2012

Filed:

Jun. 09, 2008
Applicants:

Maud Pierrel, Istres, FR;

Bilal Manai, Aix en Provence, FR;

Inventors:

Maud Pierrel, Istres, FR;

Bilal Manai, Aix en Provence, FR;

Assignee:

Atmel Rousset S.A.S., Rousset, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are placed on the MOSFET such that the distances between drains, sources, and gates are optimized to reduce resistance and power dissipation. The gates may be arranged in a trapezoidal arrangement in order to maximize a ratio of the gate widths to gate lengths for current driving while reducing resistance and power dissipation.


Find Patent Forward Citations

Pierrel, Maud. (2012). Low resistance integrated mos structure (U.S. Patent No. 8148754). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8148754

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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