Two-step hardmask fabrication methodology for silicon waveguides

Abstract

Techniques are disclosed for efficiently fabricating semiconductors including waveguide structures. In particular, a two-step hardmask technology is provided that enables a stable etch base within semiconductor processing environments, such as the CMOS fabrication environment. The process is two-step in that there is deposition of a two-layer hardmask, followed by a first photolithographic pattern, followed by a first silicon etch, then a second photolithographic pattern, and then a second silicon etch. The process can be used, for example, to form a waveguide structure having both ridge and channel configurations, or a waveguide (ridge and/or channel) and a salicide heater structure, all achieved using the same hardmask. The second photolithographic pattern allows for the formation of the lower electrical contacts to the waveguides (or other structures) without a complicated rework of the hardmask.