Integrated circuit and method for testing memory on the integrated circuit

Abstract

An integrated circuit and method for testing memory on the integrated circuit are provided. The integrated circuit has processing logic for performing data processing operations on data, and a plurality of memory units for storing data for access by the processing logic. Further, memory test logic is provided to perform a sequence of tests in order to seek to detect memory defects in the memory units. The memory test logic comprises a plurality of test wrapper units, each test wrapper unit associated with one of the memory units and being operable to execute tests on the associated memory unit, and a test controller for controlling performance of the sequence of tests by communicating with each of the test wrapper units to provide test data defining each test to be executed by that test wrapper unit. Further, a first communication link is provided for connecting each of the test wrapper units directly to the test controller, and a second communication link is provided for connecting each test wrapper unit in an ordered sequence with the test controller. When controlling performance of the sequence of tests, the test controller provides first test data via the first communication link and second test data via the second communication link. It has been found that such an approach provides a particularly efficient and flexible technique for performing BIST functions within the integrated circuit.