Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit

Abstract

A data processing circuit has an execution circuit () with a plurality of functional units (). An instruction decoder () is operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of the functional units (), and in the second instruction mode instructions control one functional unit. A mode control circuit () controls the selection of the instruction modes. In an embodiment, the instruction decoder uses time-stationary decoding of the selection of operations to be executed by the execution circuit () and the selection of destination registers from the set of registers (). Mode switching is a more efficient way of reducing instruction time for time stationary processors than indicating functional units for which the instruction contains commands. When instructions are scheduled, constraints are preferably imposed on operations for which operation selection and destination register selection are included on different sides of an instruction mode change. Such operations are avoided in an embodiment. In another embodiment, selected operations are scheduled for which operation selection and destination register selection are included on different sides of an instruction mode change. When an instruction containing a jump is encountered, the mode control circuit sets the instruction mode for subsequent instructions in conformity with information provided by the execution of the jump command.