Matrix processor data switch routing systems and methods

Abstract

According to some embodiments, an integrated circuit comprises a microprocessor matrix of mesh-interconnected matrix processors. Each processor comprises a data switch including a data switch link register and matrix routing logic. The data switch link register includes one or more matrix link-enable register fields specifying a link enable status (e.g. a message-independent, p-to-p, and/or broadcast link enable status) for each inter-processor matrix link of the processor. The matrix routing logic routes inter-processor messages according to the matrix link-enable register field(s). A particular link may be selected by a current matrix processor by selecting an ordered list of matrix links according to a relationship between ΔH and ΔV, and choosing the first enabled link in the selected list for routing. ΔH is the horizontal matrix position difference between the current (sender) processor and a destination processor, and ΔV is the vertical matrix position difference between the current and destination processors.