The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2012

Filed:

Feb. 26, 2009
Applicant:

Hitoshi Kai, Kanagawa, JP;

Inventor:

Hitoshi Kai, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An address translation circuit includes an area address holding section, an invert flag holding section, a match detection section, and a bit conversion section. The area address holding section holds at least part of a translation target address as an area address. The invert flag holding section holds an invert flag specifying whether or not part of said translation target address is to be inverted. The match detection section detects a match between a predetermined part of at least one bit in an input address on the one hand, and said area address held by said area address holding section on the other hand. If a match is detected by said match detection section and if said invert flag held by said invert flag holding section specifies that part of said translation target address is to be inverted, the bit inversion section inverts a predetermined bit part in said input address before outputting the bit-inverted address.


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