The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8143119 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 27, 2012

Filed:

Sep. 14, 2009
Applicants:

Takashi Sakoh, Kanagawa, JP;

Hiroki Shirai, Kanagawa, JP;

Inventors:

Takashi Sakoh, Kanagawa, JP;

Hiroki Shirai, Kanagawa, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A first transistor and a second transistor are formed in a first element formation region, and a third transistor is formed in a second element formation region. The three transistors are of the same conductive type, and the first transistor and the second transistor have the same threshold voltage. A first well is formed in the first element formation region by use of a first mask pattern, and a second well is formed in the second element formation region by use of a second mask pattern. A channel region of the first transistor and a channel region of the second transistor have a shape which is line-symmetrical with respect to a reference line. The first mask pattern has a shape which is line-symmetrical with respect to the reference line.


Find Patent Forward Citations

Sakoh, Takashi. (2012). Method of manufacturing semiconductor device having plural transistors formed in well region and semiconductor device (U.S. Patent No. 8143119). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8143119

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