The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2012
Filed:
Jul. 05, 2007
Takumi Okamoto, Tokyo, JP;
Takumi Okamoto, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A hierarchical design apparatusfor a semiconductor integrated circuit includes a hierarchical block placing unit-which places sets of hierarchical blocks onto a chip; a hierarchical block terminal placing unit-which places terminals of the hierarchical blocks so that for sets of hierarchical blocks having the same function, the hierarchical blocks coincide with each other in a coordinate of the corresponding terminal; an intra-hierarchical block layout unit-which executes the individual types of intra-hierarchical-block layout designs, meanwhile executes only a single type of intra-hierarchical-block layout design for the sets of hierarchical blocks having the same function; and a chip layout finishing unit-which replicates thus-obtained layout patterns, and thereby completing a layout design over the entire chip.