The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2012
Filed:
Aug. 10, 2009
Eric A. Foreman, Essex Junction, VT (US);
Peter A. Habitz, Essex Junction, VT (US);
David J. Hathaway, Essex Junction, VT (US);
Jeffrey G. Hemmett, Essex Junction, VT (US);
Kerim Kalafala, Hopewell Junction, NY (US);
Jeffrey P. Soreff, Hopewell Junction, NY (US);
Eric A. Foreman, Essex Junction, VT (US);
Peter A. Habitz, Essex Junction, VT (US);
David J. Hathaway, Essex Junction, VT (US);
Jeffrey G. Hemmett, Essex Junction, VT (US);
Kerim Kalafala, Hopewell Junction, NY (US);
Jeffrey P. Soreff, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.