The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2012

Filed:

Jan. 27, 2009
Applicants:

Zhihong Zhao, Salem, NH (US);

Aditya Agrawal, Cambridge, MA (US);

Beth Cockerham, Melrose, MA (US);

Vijay Raghavan, Framingham, MA (US);

Inventors:

Zhihong Zhao, Salem, NH (US);

Aditya Agrawal, Cambridge, MA (US);

Beth Cockerham, Melrose, MA (US);

Vijay Raghavan, Framingham, MA (US);

Assignee:

The MathWorks, Inc., Natick, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a state diagramming environment in a computing device that enables the conversion of a state diagram into a hardware description language. To achieve this conversion, the present invention generates an intermediate representation of the state diagram. The intermediate representation is checked against a set of predefined restrictions for compliance. The state diagramming environment converts the intermediate representation of the state diagram into a hardware description language, such as VHDL or Verilog.


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