The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2012
Filed:
Jul. 01, 2008
Peter L. Buchmann, Wald, CH;
Frank D. Ferraiolo, New Windsor, NY (US);
Kevin C. Gower, LaGrangeville, NY (US);
Robert J. Reese, Austin, TX (US);
Eric E. Retter, Austin, TX (US);
Martin L. Schmatz, Rueschlikon, CH;
Michael B. Spear, Round Rock, TX (US);
Peter M. Thomsen, Hutto, TX (US);
Michael R. Trombley, Cary, NC (US);
Peter L. Buchmann, Wald, CH;
Frank D. Ferraiolo, New Windsor, NY (US);
Kevin C. Gower, LaGrangeville, NY (US);
Robert J. Reese, Austin, TX (US);
Eric E. Retter, Austin, TX (US);
Martin L. Schmatz, Rueschlikon, CH;
Michael B. Spear, Round Rock, TX (US);
Peter M. Thomsen, Hutto, TX (US);
Michael R. Trombley, Cary, NC (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.