The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2012

Filed:

Sep. 02, 2004
Applicants:

Paul A. Underbrink, Lake Forest, CA (US);

Henry D. Falk, Long Beach, CA (US);

Steven A. Gronemeyer, Cedar Rapids, IA (US);

Chittharanjan A. Dassannacharya, Bangalore, IN;

Charles P. Norman, Huntington Beach, CA (US);

Nicolas Vantalon, Nice, FR;

Vojislav Protic, Palo Alto, CA (US);

Inventors:

Paul A. Underbrink, Lake Forest, CA (US);

Henry D. Falk, Long Beach, CA (US);

Steven A. Gronemeyer, Cedar Rapids, IA (US);

Chittharanjan A. Dassannacharya, Bangalore, IN;

Charles P. Norman, Huntington Beach, CA (US);

Nicolas Vantalon, Nice, FR;

Vojislav Protic, Palo Alto, CA (US);

Assignee:

CSR Technology Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01S 19/24 (2010.01);
U.S. Cl.
CPC ...
Abstract

A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at least one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.


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