The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2012

Filed:

Jul. 22, 2010
Applicants:

Ansuya P. Bhatt, Cupertino, CA (US);

Raminder Jit Singh, San Jose, CA (US);

Adam Abed, Sunnyvale, CA (US);

David A. Beeson, Pleasanton, CA (US);

Inventors:

Ansuya P. Bhatt, Cupertino, CA (US);

Raminder Jit Singh, San Jose, CA (US);

Adam Abed, Sunnyvale, CA (US);

David A. Beeson, Pleasanton, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuit and method for signal amplification is provided. The circuit includes an amplifier including an input amplifier that is arranged to receive an input analog signal, and to provide an input amplifier output signal by amplifying the input analog signal. The amplifier further includes a DC offset correction circuit that is arranged to determine a DC offset correction for the input amplifier each time the amplifier is powered up. The DC offset correction is performed by iteratively adjusting a DC offset of the input amplifier until the input amplifier output DC offset is zero when the input analog AC signal is zero, within a predetermined tolerance. The DC offset correction circuit is further arranged to provide the determined DC offset correction to the input amplifier during operation of the amplifier.


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