The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2012
Filed:
Sep. 18, 2009
Jie Chen, Saratoga, CA (US);
Ting-yen Chiang, Palo Alto, CA (US);
Kuang-yu Chen, Saratoga, CA (US);
Chen Yu Wang, San Jose, CA (US);
Joe Froniewski, Palo Alto, CA (US);
Jie Chen, Saratoga, CA (US);
Ting-Yen Chiang, Palo Alto, CA (US);
Kuang-Yu Chen, Saratoga, CA (US);
Chen Yu Wang, San Jose, CA (US);
Joe Froniewski, Palo Alto, CA (US);
Silego Technology, Inc., Santa Clara, CA (US);
Abstract
A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.