The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2012

Filed:

Sep. 25, 2007
Applicant:

Anton Salfelner, Pernegg, AT;

Inventor:

Anton Salfelner, Pernegg, AT;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 19/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system comprises a chip () and a substrate (). The chip () comprises a circuitry and a mounting surface () with first and second contacts (). The substrate () comprises a surface () with first and second contact pads () and an electrically conductive pad () connected to the first contact pad () by a low-resistive connection (). The chip () is attached to the substrate () so that the mounting surface () is spaced apart from the first contact pad () and the electrically conductive pad (). The mounting surface () overlaps partly the first contact pad () with a first overlapping area (B) resulting in a first stray capacitor (C) and the electrically conductive pad () with a second overlapping area (B) resulting in a second stray capacitor (C). The first contact pad () and the electrically conductive pad () are arranged on the surface () of the substrate () such that, if the chip () is misaligned laterally in respect to the surface (), then the first overlapping area (B) increases while the second overlapping area (B) decreases, or the first overlapping area (B) decreases while the second overlapping area (B) increases.


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