The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2012
Filed:
Aug. 28, 2008
Paul M. Steinmetz, Holly Springs, NC (US);
Benjamin J. Bowers, Cary, NC (US);
Anthony Correale, Jr., Raleigh, NC (US);
Irfan Rashid, Cary, NC (US);
Matthew W. Baker, Holly Springs, NC (US);
Paul M. Steinmetz, Holly Springs, NC (US);
Benjamin J. Bowers, Cary, NC (US);
Anthony Correale, Jr., Raleigh, NC (US);
Irfan Rashid, Cary, NC (US);
Matthew W. Baker, Holly Springs, NC (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Embodiments that reassemble hierarchical representations in a closed-loop 1×N system are disclosed. Some embodiments comprise creating a flat netlist from a hierarchical representation of a 1×N building block, creating attributes for the flat netlist, and altering one or more elements of the flat netlist, such as by an operation of a logic design tool, a synthesis tool, a physical design tool, or a timing analysis tool. The embodiments further comprise generating a second hierarchical representation of the 1×N building block that reflects the altered element. Further embodiments comprise an apparatus having a 1×N compiler and a reassembler. The 1×N compiler may create attributes for a flat netlist of elements of a hierarchical representation of a 1×N building block. The reassembler may use the attributes to create a second hierarchical representation of the 1×N building block that reflects alteration of elements to the flat netlist.