Circuit arrangement and method for error detection and arrangement for monitoring of a digital circuit

Abstract

A circuit arrangement is formed as follows. A combinational circuit has n binary inputs E, . . . , En for inputting n (n≧2) information bits x, . . . , xn and m binary outputs for outputting m (m≧1) check bits c, . . . , cm. The combinational circuit is configured for realizing a Boolean function ci=fi(xi, . . . , xini) for i=1, . . . , m at the i-th output for determining a check bit ci, wherein the set {xi, . . . , xini} at the ni information bits that determine the check bit ci is a subset of all n information bits {x, . . . , xn}. The combinational circuit is furthermore configured for realizing a first Boolean function f(x, . . . , xn) of the form c=f(x, . . . , xn)=f(x, x) XOR f(x, x) XOR . . . XOR fk(x(n−1), xn) at a first output for outputting a first check bit c, wherein nis an even number where n≧2 and 2 k=nand the Boolean functions f(x, x), . . . , fk(x(n−1), xn) are in each case nonlinear Boolean functions of two variables which can be realized by logic gates having two inputs and one output, wherein the logic gates each have a controlling value c, . . . , ck