The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2012
Filed:
Jan. 27, 2010
Schuyler E. Shimanek, Albuquerque, NM (US);
Mikhail A. Wolf, Albuquerque, NM (US);
Sanford L. Helton, San Jose, CA (US);
John G. O'dwyer, Maynooth, IE;
Schuyler E. Shimanek, Albuquerque, NM (US);
Mikhail A. Wolf, Albuquerque, NM (US);
Sanford L. Helton, San Jose, CA (US);
John G. O'Dwyer, Maynooth, IE;
Xilinx, Inc., San Jose, CA (US);
Abstract
A method of calibrating memory controller signals within an integrated circuit (IC) can include determining an internal delay of a clock network of the IC and generating a calibrated clock signal by applying a first delay to an uncalibrated clock signal, wherein the first delay is determined by subtracting the internal delay of the clock network of the IC from a bitperiod of the uncalibrated clock signal. The method can include determining a classification of at least one data signal according to timing of positive and negative edges of the at least one data signal in comparison with edges of the calibrated clock signal and aligning at least one of positive or negative edges of the at least one data signal to occur at midpoints between edges of the calibrated clock signal according to the classification of the at least one data signal.